Open AccessDESIGN TIMED FSM WITH VHDL MOORE PATTERN
Author(s) -
Marina Miroshnyk,
Alexander Shkil,
Elvira Kulak,
Dariia Rakhlis,
Anatolii Mіroshnyk,
N. V. Malahov
Publication year - 2020
Publication title -
radìoelektronìka, ìnformatika, upravlìnnâ/radìoelektronika, ìnformatika, upravlìnnâ
Language(s) - English
Resource type - Journals
eISSN - 2313-688X
pISSN - 1607-3274
DOI - 10.15588/1607-3274-2020-2-14
Subject(s) - vhdl , computer science , field programmable gate array , hardware description language , complex programmable logic device , finite state machine , embedded system , programmable logic device , computer architecture , computer hardware , programming language