Verification of a Fabless Device Model Using TCAD Tools: from Bipolar Transistor Formation to I-V Characteristics Extraction

This paper describes the analysis of processes used in microand nanoelectronic device manufacturing. It also presents an exemplary and novel laboratory exercise in which an epitaxial planar n + pn bipolar transistor with junction isolation is illustrated and analyzed stepbystep. Only seven photolithography steps are used to obtain this bipolar transistor structure: for buried layer formation, for junction transistor isolation and collectors regions formation, for base region formation, for emitter and collector n+ region formation, for contact windows, for first aluminum metallization, and, finally, for passivation. Silvaco TCAD software tools are used to implement all of these manufacturing processes and to simulate the resulting IV characteristics of all presented semiconductor structures. This type of laboratory work provides students with basic knowledge and a consistent understanding of bipolar transistor manufacturing, as well as facilitating theoretical understanding, analysis, and simulation of various semiconductor manufacturing processes without the need for costly and lengthy technological manufacturing experiments. This article also presents the conclusions and other benefits of such laboratory work, as well as possible recommendations for further improvement or expansion.