Open AccessSpecial regularities for lowering temperature during growth of high-quality CdTe semiconductor layers
Author(s) -
Pavel Moskvin,
L.V. Rashkovetskyi,
S. V. Plyatsko,
S.P. Semenets
Publication year - 2022
Publication title -
semiconductor physics, quantum electronics and optoelectronics/semiconductor physics quantum electronics and optoelectronics
Language(s) - English
Resource type - Journals
eISSN - 1605-6582
pISSN - 1560-8034
DOI - 10.15407/spqeo25.01.036
Subject(s) - cadmium telluride photovoltaics , epitaxy , semiconductor , materials science , growth rate , diffusion , constant (computer programming) , process (computing) , crystallization , phase (matter) , chemical physics , thermodynamics , optoelectronics , chemistry , nanotechnology , layer (electronics) , computer science , mathematics , physics , geometry , organic chemistry , programming language , operating system
To obtain epitaxial layers of A2B6 semiconductors with increased structural perfection from their own liquid phase, it has been proposed to use a technological process in which the synthesis temperature varies in such a manner that ensures a constant growth rate of layers during the whole process. The regularities of temperature variation with time for this process have been found on the basis of diffusion crystallization model. The developed model is realized by numerical methods and applied to description of the growth of cadmium telluride layers. Quantitative data on variations of synthesis temperature have been obtained, which can serve as a basis for choosing the temperature-time regimes of growth of cadmium telluride layers with a constant and required rate of solid phase formation.