Open AccessFPGA Implementation of Multi-scale Face Detection Using HOG Features and SVM Classifier
Author(s) -
Michał Drożdż,
Tomasz Kryjak
Publication year - 2016
Publication title -
image processing and communications
Language(s) - English
Resource type - Journals
eISSN - 2300-8709
pISSN - 1425-140X
DOI - 10.1515/ipc-2016-0014
Subject(s) - computer science , field programmable gate array , support vector machine , artificial intelligence , face detection , classifier (uml) , sliding window protocol , computer vision , facial recognition system , computation , pattern recognition (psychology) , image processing , face (sociological concept) , embedded system , window (computing) , image (mathematics) , operating system , algorithm , social science , sociology
In this paper an FPGA based embedded vision system for face detection is presented. The sliding detection window, HOG+SVM algorithm and multi-scale image processing were used and extensively described. The applied computation parallelizations allowed to obtain real-time processing of a 1280 × 720 @ 50Hz video stream. The presented module has been verified on the Zybo development board with Zynq SoC device from Xilinx. It can be used in a vast number of vision systems, including diver fatigue monitoring.