Open AccessPerformance Analysis of FPGA Based MAC Unit using DBTNS Multiplier & TRNS Adder for Signal Processing Algorithm
Author(s) -
Aniruddha Ghosh,
Amitabha Sinha
Publication year - 2018
Publication title -
advances in image and video processing
Language(s) - English
Resource type - Journals
ISSN - 2054-7412
DOI - 10.14738/aivp.65.5394
Subject(s) - adder , computer science , digital signal processing , multiplier (economics) , computer hardware , carry save adder , field programmable gate array , signal processing , binary number , booth's multiplication algorithm , arithmetic , digital signal processor , parallel computing , algorithm , mathematics , latency (audio) , telecommunications , economics , macroeconomics