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Digital Hardware Pulse-Mode RBFNN with Hybrid On-chip Learning Algorithm Based Edge Detection.
Author(s) -
Amir Gargouri,
Dorra Sellami Masmoudi
Publication year - 2012
Publication title -
journal of advanced computer science and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-4332
DOI - 10.14419/jacst.v2i1.547
Subject(s) - computer science , field programmable gate array , scalability , virtex , algorithm , process (computing) , artificial neural network , hardware acceleration , chip , computer hardware , enhanced data rates for gsm evolution , artificial intelligence , telecommunications , database , operating system

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