Open AccessDiminished-1 multiplier using modulo adder
Author(s) -
Beerendra Kumar Patel,
Jitendra Kanung
Publication year - 2018
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i4.20.22117
Subject(s) - adder , modulo , arithmetic , multiplier (economics) , operand , carry save adder , mathematics , serial binary adder , modulo operation , block (permutation group theory) , computer science , algorithm , discrete mathematics , combinatorics , telecommunications , economics , macroeconomics , latency (audio)
In this work Modulo multiplier offers higher computational speed than a normal multiplier. It is frequently used in data security and residue number system. The modulo 122n+1"> has three basic blocks-partial product generation block, inverted end around carry adder tree block and diminished-1 modulo 122n+1"> adder block. The result and an operand use weighted representation and others uses the diminished-1 for the modulo multiplier. The multipliers receive full inputs and avoid (n+1) bits circuits due to diminished-1 number representation. In this work, proposed modulo 122n+1"> multiplier with modified diminished-1 modulo 122n+1"> adder which is based on ripple carry adder. The proposed design saves significant area and power as compared to the reported one with little increment in delay.