Open AccessSymmetric stacked fast binary counters based on reversible logic
Author(s) -
C. Santhi,
Moparthy Gurunadha Babu
Publication year - 2018
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i4.14141
Subject(s) - digital electronics , dissipation , binary number , electronic circuit , logic gate , computer science , sequential logic , electronic engineering , pass transistor logic , adiabatic circuit , electrical engineering , algorithm , engineering , physics , arithmetic , mathematics , thermodynamics
A Symmetric Stacked Fast Binary counter design is proposed in this paper. In the circuit design, the first phase is occupied by 3-bit stacking circuits, which are further followed by combining circuits. The resultant novel circuit thus becomes a 6-bit stacker. A 6:3 counter has been chosen as an example to demonstrate the working of the proposed circuit. The proposed circuit is further implemented by using reversible logic gates. Heat dissipation is a major problem in the designing of a digital circuit. Rolf Landauer has proved that the information loss in a digital circuit is directly proportional to the energy dissipation. The proposed modified Symmetric Stacking counter is implemented using reversible logic gates thus reducing the power dissipation of the circuit.