Open AccessLow leakage SRAM cell for ULP applications
Author(s) -
Tripti Tripathi,
Durg Singh Chauhan,
Sanjay Kumar Singh
Publication year - 2018
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i4.14028
Subject(s) - leakage (economics) , leakage power , standby power , static random access memory , transistor , electronic engineering , electrical engineering , cadence , power (physics) , computer science , embedded system , engineering , voltage , physics , quantum mechanics , economics , macroeconomics
Leakage power is becoming a major concern in battery operated and hand held devices. With the ever reducing size of electronic devices and the use of memory in most of them, the need for low power devices is vastly increasing. These devices are either in active or standby mode of operation. Leakage power in standby mode of operation is of major concern and various methods to minimize it have been proposed at various stages of design cycle. This paper proposes fingering technique that can be used in 6T SRAM cell to reduce leakage power. Leakage power is calculated for 6T SRAM cell designed using two fingers in access transistors and on comparison with conventional 6T SRAM cell, significant reduction in leakage current is obtained. The layout has been designed in UMC 55nm technology using Cadence Virtuoso tool and it has been shown that the leakage power and delay can be reduced.