Open AccessFPGA implementation of 1000base-x Ethernet physical layer core
Author(s) -
Eman Salem,
Abdelhalim Zekry,
Hossam Labeb,
Radwa Tawfik
Publication year - 2018
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i4.13469
Subject(s) - field programmable gate array , vhdl , physical layer , gigabit ethernet , phy , transceiver , embedded system , ethernet , computer science , fiber distributed data interface , computer hardware , telecommunications , wireless
This paper introduces the field programmable gate array FPGA implementation of 1000BASE-X PHY Physical Layer for gigabit Ethernet over fiber optic cable. The implementation is achieved by developing VHDL model for all its building blocks including the physical coding sub layer, PCS, and the physical medium attachment, PMA. The VHDL code is simulated using XILINX ISE14.7 and synthesized on Xilinx Virtex6 FPGA chip. Measured results show that the designed and implemented Ethernet transceiver works successfully at 1.32 Gb/s, 2.5V supply with reduced power consumption.