Open AccessReview on Architectures of Motion Estimation for Video Coding Standards
Author(s) -
Prayline Rajabai C,
S. Sivanantham
Publication year - 2018
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i4.10.26629
Subject(s) - computer science , motion estimation , codec , quarter pixel motion , motion compensation , data compression , video compression picture types , multiview video coding , coding (social sciences) , rate–distortion optimization , block matching algorithm , reference frame , inter frame , compression ratio , video processing , computer hardware , real time computing , computer vision , video tracking , frame (networking) , telecommunications , statistics , mathematics , engineering , automotive engineering , internal combustion engine
Various video coding standards like H.264 and H.265 are used for video compression and decompression. These coding standards use multiple modules to perform video compression. Motion Estimation (ME) is one of the critical blocks in the video codec which requires extensive computation. Hence it is computationally complex, it critically consumes a massive amount of time to process the video data. Motion Estimation is the process which improves the compression efficiency of these coding standards by determining the minimum distortion between the current frame and the reference frame. For the past two decades, various Motion Estimation algorithms are implemented in hardware and research is still going on for realizing an optimized hardware solution for this critical module. Efficient implementation of ME in hardware is essential for high-resolution video applications such as HDTV to increase the decoding throughput and to achieve high compression ratio. A review and analysis of various hardware architectures of ME used for H.264 and H.265 coding standards is presented in this paper.