Open AccessEfficient design of chaos based 4 bit true random number generator on FPGA
Author(s) -
Ramji Gupta,
Alpana Pandey,
R. K. Baghel
Publication year - 2018
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i3.16586
Subject(s) - nist , random number generation , field programmable gate array , computer science , cryptography , generator (circuit theory) , 8 bit , self shrinking generator , chaos (operating system) , block (permutation group theory) , chaotic , embedded system , computer hardware , algorithm , mathematics , electrical engineering , power (physics) , engineering , physics , induction generator , geometry , computer security , quantum mechanics , artificial intelligence , wind power , natural language processing
True random number generator is a basic building block of any modern secure communication and cryptography system. FPGA implementation of any system has a flexible architecture and low-cost test cycle. In this paper, we present an FPGA implementation of a high speed true random number generator based on chaos oscillator which gives optimize ratio of bit rate to area. The proposed generator is faster and more compact than the existing chaotic oscillator based TRNGs. The Experimental result shows that the proposed TRNG gives 1439 Mbps with optimizing the use of LUTs and registers. It is verified that the generator passes all the NIST SP 800-22 tests. The proposed TRNG is implemented in two FPGA families Nexus 4 (Artix 7) DDR XC7A100TCSG-1 and Basys 3 XC7A35T1CPG236C (Artix 7) using Xilinx Vivado v.2017.3 design suite.