Open AccessEnergy Efficient VLSI Architecture for Variable Iterative 4G LTE Turbo Decoder
Author(s) -
K. N. Manjunatha,
Vaibhav Meshram
Publication year - 2018
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i3.12652
Subject(s) - computer science , decoding methods , turbo code , very large scale integration , cmos , maximum a posteriori estimation , dissipation , algorithm , critical path method , chip , latency (audio) , turbo , parallel computing , electronic engineering , computer engineering , embedded system , mathematics , engineering , telecommunications , maximum likelihood , statistics , physics , thermodynamics , systems engineering , automotive engineering
The Long Term Evolution (LTE) networks main objective is to support the next generation wireless communication systems. But most of the LTE approaches are suffer from decoding latency. Hence results in drop of data rate and this is not supported by the 4G LTE standards. To overcome this few parallel architectures has been introduced with the cost of power and silicon chip area. One promising decoding algorithm to overcome the decoding latency is Maximum a Posteriori (MAP) algorithm. The MAP has two computationally challenging α and β units. These two units have critical path and are to be reduced. A novel architecture for Add-Compare-Select (ACS) is proposed with clock gating techniques to reduce the unnecessary power dissipation across the recursive computational units. The proposed technique is applied with max-log MAP algorithm to precise the approximation. The overall design in implemented in a 45nm CMOS technology and results in 179.2mW of power dissipation which results in 34.6% less power compared to reported design while monitoring the moderate or same throughput level.