Open AccessDesign, Implementation and Analysis of 8T SRAM Cell in Memory Array
Author(s) -
B Kaleeswari,
S. Kaja Mohideen
Publication year - 2018
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i3.1.16808
Subject(s) - static random access memory , schematic , computer science , leakage power , very large scale integration , leakage (economics) , power consumption , memory cell , embedded system , electronic engineering , power (physics) , transistor , computer hardware , electrical engineering , engineering , voltage , physics , quantum mechanics , economics , macroeconomics
In modern VLSI designs, static random access memory plays a vital role because of its high performance and low power consumption qualities. As technology is scale down, the importance of the power analysis and leakage current of memory design is increasing. This paper describes about the 1 KB size memory design using SRAM. The proposed design of 8T SRAM single cell in implemented in array structure of size 32x32.The design structure reduces the power by 75% by reducing the leakage current. The proposed 8T SRAM cell is implemented and analyzed in 90nm technology using Digital schematic and Micro wind software.