Open AccessReview a Low Power CMOS Charge Pump using Power Gating Techniques to Reduce Leakage Power
Author(s) -
N Vengadeswari,
Priscilla Whitin
Publication year - 2018
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i3.1.16790
Subject(s) - charge pump , power gating , electrical engineering , capacitor , electronic circuit , parasitic capacitance , leakage (economics) , cmos , materials science , voltage , capacitance , electronic engineering , engineering , transistor , physics , electrode , quantum mechanics , economics , macroeconomics
In most case, charge pump circuit is designed based on capacitor, where voltage is increased at each stage depending on each stage voltage gain. Major elements are all charge pumps circuits one is Pumping capacitors and diode connected MOS.To increases pumping efficiency is very higher for each stage of charge pump circuits. Pumping efficiency are limiting by two parameters one is parasitic capacitance and threshold voltage. The power dissipated from the circuit can be increased by attain of leakage current .To resist this leakage in the circuits the supply voltage is major concern. To reduce the leakage with the help of power gating technique .Charge pump circuits are to be designed and verified by using tanner t-spice tools.