Open AccessImplementation of reconfigurable galois field multipliers over2m using primitive polynomials
Author(s) -
B Raj Narain,
T. Sasilatha
Publication year - 2018
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i2.12.11356
Subject(s) - galois theory , multiplier (economics) , field programmable gate array , bitwise operation , finite field , mathematics , computer science , normal basis , arithmetic , discrete mathematics , computer hardware , economics , macroeconomics , programming language
The Galois field multiplier finds extensive use in cryptographic solutions and applications. The Galois field multiplier can be implemented as fixed bitwise or reconfigurable. For fixed length, the data is restricted to the fixed length. But in reconfigurable GF multipliers, the bit length of the multiplier is flexible and is independent of hardware architecture. This paper proposes a method to implement a reconfigurable GF multiplier for various bit values from 8 to 128 bits. This paper compares the area complexity of various bit size in Xilinx Spartan 3E family FPGA and estimates the resources required for the implementation.