Open Access10Ghz Charge Pump PLL for Low Jitter Applica-tions
Author(s) -
D S Rajeshwari,
P. V. Rao,
Ramesh Karmungi
Publication year - 2018
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i2.12.11349
Subject(s) - jitter , voltage controlled oscillator , charge pump , phase locked loop , electrical engineering , voltage , cascode , physics , computer science , engineering , capacitor , transistor
This paper presents design and simulation of charge pump architectures for 10GHz Charge Pump Phase locked Loop. Differential delay cell VCO with symmetric load and Programmable frequency divider are efficiently implemented in loop. Able to achieve Peak jitter of the Divider 10ns, Peak jitter of VCO 205ps at 1GHz.Charge pump is analysed in loop by reduced current mismatch using improved high swing cascode structure including start up circuitand it has low turn ON voltage and high ouput impedance to provide stable voltage.Charge pump results current mismatch less than 0.05%.10GHz DPLL is simulated with 65nm techonology, 1.2V and tsmc foundary model files