Open AccessImplementation of 16 Bit SAR ADC in CMOS and sub threshold cml techniques
Author(s) -
K. A. Jyotsna,
P Satish Kumar,
B. K. Madhavi,
I Swaroopa
Publication year - 2018
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i2.12.11298
Subject(s) - cmos , comparator , successive approximation adc , computer science , interfacing , schematic , electronic engineering , electrical engineering , transistor , voltage , computer hardware , engineering
The trends of the VLSI technology is advancing, due to this majority of the industry players are showing interest in development of the devices with ultra low power applications. Analog-to-Digital converters are getting extensively used in Medical implant machines and in lots of Sensor machines, because it is serving an imperative role in interfacing between analog signal and digital signal. This paper presents a modernistic technique called as Sub threshold Current Mode Logic (CML) for ultra low power digital components. Here 16 bit SAR ADC is designed and compared with the techniques like CMOS and STCML for power consumption and delay. Schematics are materialized with Cadence Virtuoso tool using 45nm process. The transistors in these CML and CMOS operate at threshold voltages and Sub-threshold voltages where the executable design is done using 1V to 0.5V power supply (VDD). The comparator dissipates aggrandized power, so most of the intension is converged on forming this chunk. The CML logic procedure operates primarily with the current domain, due to this the performance can be constitutionally high. This approach decreases static power dissipation.