Open AccessImplementation of data path components of ARM7 microprocessor using sub threshold current mode logic with sleep transistor technique
Author(s) -
K. A. Jyotsna,
P Satish Kumar,
B. K. Madhavi,
Sana Bano
Publication year - 2018
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i2.12.11292
Subject(s) - microprocessor , transistor , sleep mode , computer science , very large scale integration , chip , cadence , electrical engineering , embedded system , current mode logic , electronic engineering , power (physics) , computer hardware , cmos , power consumption , engineering , voltage , physics , quantum mechanics
The latest Very Large Scale Integration (VLSI) technology trends have been moving towards making devices cheaper and more powerful for everyone to afford them. So the ultimate focus being reducing power consumption by the gadgets. With the added feature of transistors to be structured in 3D, the Moore’s law is to be continued. Hence, Leakage currents are a major concern with the increasing number of transistors per chip when the technology is scaled, static power dissipation needs to be monitored. Advanced RISC Machine (ARM) Processors have been giving a new definition to smart phones, tablets and other embedded applications. This paper presents a novel technique focusing on low power technology, developing an ARM7 microprocessor using Sleep transistor with Sub threshold Current Mode Logic (STCML) technique in 45nm technology using Cadence Virtuoso Tool. The simulation results have been observed on Spectre simulator and power has been calculated in Analog Design Environment (ADE L).