Open AccessPerformance evaluation of heuristic algorithms in floor planning for ASIC design
Author(s) -
S. Nazeer Hussain,
K. Hari Kishore
Publication year - 2017
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i1.5.9122
Subject(s) - very large scale integration , floor plan , simulated annealing , computer science , tabu search , algorithm , plan (archaeology) , heuristic , application specific integrated circuit , mathematical optimization , engineering drawing , mathematics , artificial intelligence , engineering , embedded system , archaeology , history
A study on physical design of VLSI Floor planning is discussed using optimization techniques for betterment in performance of VLSI chip. Floor planning in VLSI is considered to be a Non Polynomial problem. Such problems can be solved using computations. The initial step in floor plan is the representation of floor plan design. The floor plan representations show greater impact on the search space and the complexity of the floor plan design. The objective of this paper is to study different algorithms that addressees the problem of handling alignment constraints such as good placement, optimum area and short run time. Different heuristic and meta-heuristic algorithms are proposed and suggested by many researchers for solving the VLSI Floor plan problem. In this paper Simulated Annealing algorithm, Ant Colony Algorithm, Tabu search and Genetic algorithms are discussed.