Open AccessA novel design of high performance1-bit adder circuit at deep sub-micron technology
Author(s) -
Venkata Rao Tirumalasetty,
C V. Mohan Krishna,
K Sai Sree Tanmaie,
T Lakshmi Naveena,
Ch Jonathan
Publication year - 2017
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i1.1.10822
Subject(s) - adder , power–delay product , cmos , transistor , computer science , electronic engineering , transistor count , pass transistor logic , logic gate , electrical engineering , serial binary adder , circuit design , xor gate , computer hardware , engineering , voltage
In this paper, the design of hybrid 1-bit full adder circuit using both pass transistor and CMOS logic was implemented. Performance pa-rameters such as power, delay, and PDP were compared with the existing designs such as complementary pass-transistor logic, transmis-sion gate adder. At 0.4V supply at 22nm technology, the average power consumption is 1. 525 uW was found to be extremely low with moderately low delay 90. 25 ps and PDP found to be 0.137 fJ. The present implementation has very good improvement in terms of delay, power and power delay product when compared to the existing hybrid 1-bit full adders. Also the number of transistors has been reduced to 13 where as the existiing hybrid full adder circuit has 16 transistors. The proposed circuit was implemented using mentor graphics tool in 45nm, 32nm and 22nm technologies with different supply voltages.