Open AccessA novel 3-D-IC test architecture-a review
Author(s) -
R. Karthick,
M Sundararajan
Publication year - 2017
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i1.1.10228
Subject(s) - crosstalk , overhead (engineering) , embedded system , built in self test , computer science , fault coverage , electronic engineering , reliability engineering , engineering , electronic circuit , electrical engineering
Here, this paper completely examines the crosstalk noise of Through-Silicon-Vias (TSVs) in high speed operations by means of a novel 3-Dimensional-IC Test structural design. In order to decline the crosstalk, the fast rise time devices have to be circumvented except they are essential for performance in some certain circuit parts. It must be noted that this system simultaneously examines the TSVs and the memory and does not require spending additional area for a test pattern generator in case of the TSV test. With the intention of reprocessing the test patterns of new-fangled memory BIST, the value of “data” or “address” need to be fixed to some specific values. In accordance with the outcomes of the TSV grouping, here also implemented a high-efficiency, low-area-overhead TSV test structural design. The amount of test cycles essential for the purpose of finding failing TSVs and regulate the fault category effectively than that in related work.