Open AccessImplementation of MHLFF based low power pulse triggered flip flop
Author(s) -
Shreya Verma,
Tunikipati Usharani,
S. ISWARIYA,
Bhavana Godavarthi
Publication year - 2017
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v7i1.1.10150
Subject(s) - flip flop , computer science , transistor , power (physics) , pulse (music) , generator (circuit theory) , lock (firearm) , electronic engineering , cadence , pulse generator , block (permutation group theory) , electrical engineering , engineering , telecommunications , jitter , voltage , physics , mathematics , enhanced data rates for gsm evolution , quantum mechanics , mechanical engineering , geometry , detector
The present research paper proposes to implement a low power pulse-triggered flip-flop. The proposed design is MHLFF (modified hybrid latch flip-flop). In MHLFF method, the pulse generator will be altered concerning illustration inverters what’s more a pasquinade transistor. This technique will be comparative should understood kind about flip flop what’s more it utilizes a static lock structure. Should succeed Most exceedingly bad situation delay issue brought on Eventually Tom's perusing discharging way comprise from claiming three stacked transistor MHLFF may be presented. We can minimize the power and delay when compared to the existing models i.e, CDFF and SCDFF. The circuit was implementing using Cadence Virtuoso tool in 90-nm and 45-nm technology.