Open AccessImplementation of a standard inner convolutional codec for DVB-T system using VHDL
Author(s) -
Dina M. Hussein,
Abdelhalim Zekry,
Said Baioumy,
Fatma El-Newagy
Publication year - 2017
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v6i4.8038
Subject(s) - convolutional code , viterbi decoder , computer science , forward error correction , codec , reed–solomon error correction , encoder , viterbi algorithm , dvb t , computer hardware , error detection and correction , burst error , turbo code , field programmable gate array , decoding methods , real time computing , channel (broadcasting) , concatenated error correction code , algorithm , telecommunications , orthogonal frequency division multiplexing , block code , operating system
Forward error correction (FEC) plays a vital role in digital communication systems. DVB-T system uses FEC as a channel coding technique to restore any data lost through transmission to the receiver. DVB-T system uses two levels of error protection. The first level is applied in the data transmitted by using a Reed-Solomon RS (204, 188) code followed by a convolutional interleaver. The other level of error protection is a punctured convolutional inner coding followed by an inner interleave in which the data sequence is rearranged again to minimize the influence of burst errors.This paper describes the implementation of inner convolutional codec (Convolutional coder and Viterbi Decoder) and inner de/interleaving of a standard DVB-T system with a constrained length of 7 and a code rate of 2/3 using VHDL on virtex-6 FPGA xc6vlx240t. The designed channel convolutional encoder and Viterbi decoder follow European Standard ETSI EN 300 744 for digital terrestrial television. Verification of the design is accomplished by loop back and by comparison with the corresponding Xilinx core. Utilization and timing re-ports of the implemented device on Vertex 6 are included.