Open AccessConception of a new LDPC decoder with hardware implementation on FPGA card
Author(s) -
Anas El Habti El Idrissi,
Rachid El Gouri,
Laamari Hlou
Publication year - 2014
Publication title -
international journal of engineering and technology
Language(s) - English
Resource type - Journals
ISSN - 2227-524X
DOI - 10.14419/ijet.v3i4.3185
Subject(s) - low density parity check code , field programmable gate array , computer science , decoding methods , parity check matrix , algorithm , coding (social sciences) , error detection and correction , parity bit , computer hardware , coding theory , soft decision decoder , code (set theory) , parallel computing , theoretical computer science , mathematics , statistics , set (abstract data type) , programming language
Low Density Parity-Check codes are one of the hottest topics in coding theory nowadays. Equipped with very fast encoding and decoding algorithms, LDPC codes are very attractive both theoretically and practically. In this paper, A simplified algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity, this algorithm is based on a simple matrix equation which must be resolved in order to calculate all possible solutions of this equation, and then a simple circuit will be used to determine the errors produced during the transmission channel. First, we developed the design of the proposed algorithm second, we generated and simulated the hardware description language source code using Quartus software tools and finally we implemented the new algorithm of LDPC codes on FPGA card. Keywords: Bit-Flipping Algorithm, Error Detection, FPGA Card, LDPC Decoder, Matrix Equation.