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Design and Implementation of 4 Bit Static RAM through Low-Power Pulse-Triggered Flip-Flop
Author(s) -
G. Suresh,
N. V. Lalitha,
R. Aamani
Publication year - 2015
Publication title -
international journal of u- and e-service, science and technology
Language(s) - English
Resource type - Journals
eISSN - 2207-9718
pISSN - 2005-4246
DOI - 10.14257/ijunesst.2015.8.9.13
Subject(s) - flip flop , computer science , bit (key) , flip , power (physics) , arithmetic , computer hardware , parallel computing , mathematics , physics , telecommunications , computer network , quantum mechanics , enhanced data rates for gsm evolution , apoptosis , biochemistry , chemistry

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