FPGA Implementation of Bit Stuffing Reduction Algorithm for CAN Communication by Miller Line Encoding Scheme
Author(s) -
Ronnie O. Serfa Juan,
Hi-Seok Kim
Publication year - 2017
Publication title -
international journal of control and automation
Language(s) - English
Resource type - Journals
eISSN - 2207-6387
pISSN - 2005-4297
DOI - 10.14257/ijca.2017.10.4.05
Subject(s) - reduction (mathematics) , scheme (mathematics) , encoding (memory) , computer science , field programmable gate array , line (geometry) , algorithm , miller , bit (key) , computer hardware , arithmetic , mathematics , computer network , artificial intelligence , biology , mathematical analysis , geometry , ecology
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