SSTL IO Standard Based Energy Efficient Digital Clock Design on 28nm FPGA
Author(s) -
Shivani Madhok,
Navdeep Singh,
Furqan Fazili,
Sumita Nagah,
Sweety Dabas,
Ravinder Kaur
Publication year - 2015
Publication title -
international journal of control and automation
Language(s) - English
Resource type - Journals
eISSN - 2207-6387
pISSN - 2005-4297
DOI - 10.14257/ijca.2015.8.6.05
Subject(s) - field programmable gate array , computer science , digital clock , embedded system , computer hardware , energy (signal processing) , computer architecture , telecommunications , physics , quantum mechanics , jitter
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