Critical pattern selection method for full-chip source and mask optimization

Source and mask optimization (SMO) is one of the most important resolution enhancement techniques for integrated circuit manufacturing in 2X nm technology node and beyond. Nowadays full-chip SMO is alternatively realized by applying SMO to limited number of selected critical patterns instead of to full-chip area, since it is too computational expensive to be apply SMO in full-chip area directly. The critical patterns are selected by a pattern selection method which enables SMO in full-chip application by balancing the performance and computation consumption. A novel diffraction-based pattern selection method has been proposed in this paper. In this method, diffraction-signatures are sufficiently described with widths in eight selected directions. Coverage rules between the diffraction-signatures are specifically designed. Diffraction-signature grouping method and pattern selection strategy are proposed based on the diffraction-signatures and coverage rules. A series of simulations and comparisons performed using ASML's Tachyon software, which is one of the state of the art commercial SMO platforms, verify the validity of the proposed method.