
FPGA implementation of rate-adaptive spatially coupled LDPC codes suitable for optical communications
Author(s) -
Xiaole Sun,
Ivan B. Djordjević
Publication year - 2019
Publication title -
optics express
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 1.394
H-Index - 271
ISSN - 1094-4087
DOI - 10.1364/oe.27.003422
Subject(s) - low density parity check code , computer science , emulation , field programmable gate array , forward error correction , coding (social sciences) , error detection and correction , decoding methods , algorithm , electronic engineering , computer hardware , mathematics , engineering , statistics , economics , economic growth
In this paper, we propose a unified field-programmable gate array (FPGA) structure for a rate-adaptive forward error correction (FEC) scheme based on spatially coupled (SC) LDPC codes derived from quasi-cyclic (QC) LDPC codes. We described the unified decoder structure in detail and showed that the rate adaptation can be achieved by a controller on-the-fly. By FPGA based emulation, the results show that, with comparable complexity, the SC codes provide larger coding gain. The implemented unified structure can be employed for any template QC-LDPC code to achieve a spatially-coupling based code-rate adaptation scheme.