Open AccessHigh-speed scrubbing demonstration using an optically reconfigurable gate array
Author(s) -
Takahiro Fujimori,
Minoru Watanabe
Publication year - 2017
Publication title -
optics express
Language(s) - Uncategorized
Resource type - Journals
SCImago Journal Rank - 1.394
H-Index - 271
ISSN - 1094-4087
DOI - 10.1364/oe.25.007807
Subject(s) - field programmable gate array , data scrubbing , mean time between failures , triple modular redundancy , redundancy (engineering) , gate array , computer science , modular design , static random access memory , computer hardware , embedded system , engineering , failure rate , reliability engineering , operating system
This paper presents a proposal for a high-speed scrubbing method based on an optically reconfigurable gate array (ORGA) architecture. A salient concern for current field programmable gate arrays (FPGAs) used in high-radiation environments is the high frequency of soft-errors occurring on their configuration memories. Even if triple modular redundancy is used for implementations on FPGAs, soft-error tolerance issues on the configuration memories cannot be alleviated. This paper therefore presents a high-speed scrubbing method that is applicable to ORGA architectures, in addition to its experimental demonstration on an ORGA-VLSI. The mean time between soft-errors (MTBF) on the ORGA configuration memory has been analyzed theoretically: the MTBF can be extended to 1.35-1.89 million times longer than those of current FPGAs.