Open AccessPattern-Integrated Interference Lithography: Prospects for Nano- and Microelectronics
Author(s) -
Matthieu C. R. Leibovici,
Guy M. Burrow,
Thomas K. Gaylord
Publication year - 2012
Publication title -
optics express
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 1.394
H-Index - 271
ISSN - 1094-4087
DOI - 10.1364/oe.20.023643
Subject(s) - lithography , design for manufacturability , interference lithography , microelectronics , interference (communication) , trim , photolithography , maskless lithography , extreme ultraviolet lithography , x ray lithography , next generation lithography , stencil lithography , computational lithography , optics , computer science , materials science , electronic engineering , resist , nanotechnology , electron beam lithography , optoelectronics , engineering , telecommunications , physics , fabrication , electrical engineering , channel (broadcasting) , medicine , alternative medicine , pathology , layer (electronics) , operating system
In recent years, limitations in optical lithography have challenged the cost-effective manufacture of nano- and microelectronic chips. Spatially regular designs have been introduced to improve manufacturability. However, regular designed layouts typically require an interference step followed by a trim step. These multiple steps increase cost and reduce yield. In the present work, Pattern-Integrated Interference Lithography (PIIL) is introduced to address this problem. PIIL is the integration of interference lithography and superposed pattern mask imaging, combining the interference and the trim into a single-exposure step. Example PIIL implementations and experimental demonstrations are presented. The degrees of freedom associated with the source, pattern mask, and Fourier filter designs are described.