Open AccessImplementation of Low Power Generic 2D FIR Filter Bank Architecture Using Memory-based Multipliers
Author(s) -
Venkata Krishna Odugu,
C. Venkata Narasimhulu,
K. Satya Prasad
Publication year - 2022
Publication title -
journal of mobile multimedia
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.229
H-Index - 12
eISSN - 1550-4654
pISSN - 1550-4646
DOI - 10.13052/jmm1550-4646.1836
Subject(s) - filter design , computer science , filter (signal processing) , block (permutation group theory) , filter bank , finite impulse response , computer hardware , verilog , cadence , electronic engineering , arithmetic , algorithm , mathematics , field programmable gate array , engineering , geometry , computer vision
In this paper, a generic filter bank architecture for 2D FIR filter is proposed using block processing, symmetry in the filter coefficients, and memory-based multipliers. The different symmetry filters are considered as sub-filters of the filter bank to decrease the number of multipliers and the desired filter can be selected using control logic to reduce the power consumption. The block processing is incorporated to increase the throughput of the filter. Due to this block processing, memory sharing and memory reuse are achieved to optimize the architecture in terms of area, memory, and power. In each filter, the conventional multipliers are replaced with Distribute Arithmetic (DA) based memory multipliers to decrease the delay, power, and area of each sub-filter. The proposed design is coded by Verilog HDL and synthesized using Cadence Genus tools in 45 nm technology. The physical design is carried out using Cadence Innovus tools. The proposed design results are compared with state-of-the-art works.