Development of a Simple Verification Environment Using FPGA for image processing Hardware Created by High-Level-Synthesis Using TCP/IP | Zendy

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Development of a Simple Verification Environment Using FPGA for image processing Hardware Created by High-Level-Synthesis Using TCP/IP

Author(s) -

Atsushi Shojima,

Akira Yamawaki

Publication year - 2021

Language(s) - English

Resource type - Conference proceedings

DOI - 10.12792/icisip2021.038

Subject(s) - field programmable gate array , computer science , simple (philosophy) , embedded system , computer hardware , image processing , image (mathematics) , artificial intelligence , philosophy , epistemology

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