Open AccessLevel Shifted Discontinuous PWM Algorithms to Minimize Common Mode Voltage for Cascaded Multilevel Inverter Fed Induction Motor Drive
Author(s) -
M. Nayeemuddin,
T. Bramhananda Reddy,
M. Vijaya Kumar
Publication year - 2018
Publication title -
international journal of power electronics and drive systems (ijpeds)
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.322
H-Index - 21
ISSN - 2088-8694
DOI - 10.11591/ijpeds.v9.i2.pp504-518
Subject(s) - pulse width modulation , common mode signal , induction motor , inverter , harmonics , control theory (sociology) , modulation (music) , computer science , voltage , dspace , motor drive , algorithm , electronic engineering , engineering , physics , digital signal processing , control (management) , electrical engineering , acoustics , mechanical engineering , artificial intelligence , analog signal
This paper presents combinations of level shifted pulse-width modulation algorithm with conventional discontinuous pulse-width modulation methods for cascaded multilevel inverters. In the proposed DPWM a zero sequence signal is injected in sinusoidal reference signal to generate various modulators with easier implementation. The analysis four various control strategies namely Common Carrier (CC), Inverted Carrier (IC), Phase Shifted (PS) and Inverted Phase Shift (IPS) for cascaded multilevel inverter fed induction motor drive has been illustrated. To validate the proposed work experimental tests has been carried out using dSPACE controller. Experimental study proves that using proposed algorithms reduction in common-mode voltage with fewer harmonics along with reduced switching loss for a cascaded multilevel inverter fed motor drive has been achieved.