Open AccessA proposed asymmetrical configuration of cascaded multilevel inverter topology for high level generation
Author(s) -
Lipika Nanda,
Chitralekha Jena,
Arjyadhara Pradhan,
Babita Panda
Publication year - 2022
Publication title -
international journal of power electronics and drive systems/international journal of electrical and computer engineering
Language(s) - English
Resource type - Journals
eISSN - 2722-2578
pISSN - 2722-256X
DOI - 10.11591/ijpeds.v13.i1.pp289-297
Subject(s) - total harmonic distortion , inverter , topology (electrical circuits) , pulse width modulation , matlab , electronic engineering , computer science , voltage , power (physics) , modulation (music) , distortion (music) , harmonic , control theory (sociology) , electrical engineering , engineering , physics , acoustics , amplifier , control (management) , quantum mechanics , artificial intelligence , operating system , cmos
Multilevel inverters are having high demand in high power applications. It works in medium voltage range. In this converter, for specific time intervals fewer switches will be conducting so switching loss is also reduced. This paper represents overall total harmonic distortion (THD) for different levels and different carrier frequencies. Switching loss, conduction loss of inverter has been discussed and hence inverter efficiency can be calculated. Phase displacement pulse width modulation method has been proposed in order to generate pulses. The proposed topology is well presented by its practical implementation with two current direct sources. All the simulations are being carried out using MATLAB/Simulink platform to validate the hardware results.