Open AccessCurrent mode control of single phase grid tie inverter with anti-islanding
Author(s) -
Sanjay Lakshminarayanan,
K.V. Pradeep Kumar,
S. Nagaraja Rao,
S Pranupa
Publication year - 2021
Publication title -
international journal of power electronics and drive systems/international journal of electrical and computer engineering
Language(s) - English
Resource type - Journals
eISSN - 2722-2578
pISSN - 2722-256X
DOI - 10.11591/ijpeds.v12.i1.pp241-248
Subject(s) - islanding , inverter , computer science , grid , control theory (sociology) , phase locked loop , matlab , current (fluid) , voltage , control (management) , electronic engineering , electrical engineering , engineering , distributed generation , telecommunications , renewable energy , geometry , mathematics , artificial intelligence , jitter , operating system
The aim of this paper is to explore the use of various current mode control (CMC) techniques to design a single phase grid tie inverter integrated with anti-islanding protection. Three types of CMC techniques have been discussed, namely current hysteresis control (CHC), constant frequency control (CFC) and average current mode control (ACMC). The performance of the grid tie inverter in the event of grid voltage failure is also studied to help install an anti-islanding mechanism. The proposed control techniques shall eliminate the use of Phase locked loop (PLL) control as the current reference is generated from the grid voltage itself. All three current mode control techniques of an inverter have been simulated in MATLAB/Simulink to evaluate the performance of the designed inverter. The simulated results show a current THD of less than 5% in all three methods and a good anti-islanding response.