Open AccessEfficient hardware implementation for lightweight mCrypton algorithm using FPGA
Author(s) -
Yasir Amer Abbas,
Ahmed Salah Hameed,
Safa Hazim Alwan,
Maryam Adnan Fadel
Publication year - 2021
Publication title -
indonesian journal of electrical engineering and computer science
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.241
H-Index - 17
eISSN - 2502-4760
pISSN - 2502-4752
DOI - 10.11591/ijeecs.v23.i3.pp1674-1680
Subject(s) - field programmable gate array , throughput , computer science , embedded system , architecture , cryptography , power consumption , wireless , computer hardware , power (physics) , algorithm , telecommunications , art , visual arts , physics , quantum mechanics
The lightweight cryptography is used for low available resources devices such as radio frequency identification (RFID) tags, internet of things (IoTs) and wireless sensor networks. In such case, the lightweight cryptographic algorithms should consider power consumption, design area, speed, and throughput. This paper presents a new architecture of mCrypton lightweight cryptographic algorithm which considers the above-mentioned conditions. Resource-shared structure is used to reduce the area of the new architecture. The proposed architecture is implemented using ISE Xilinx V14,5 and Spartan 3 FPGA platform. The simulation results introduced that the proposed design area is 375 of slices, up to 302 MHz operating frequency, a throughput of 646 Mbps, efficiency of 1.7 Mbps/slice and 0.089 Watt power consumption. Thus, the proposed architecture outperforms similar architectures in terms of area, speed, efficiency and throughput.