Open AccessDesign and analysis of RNS-based sign detector for moduli set {2^n, 2^n - 1, 2^n + 1}
Author(s) -
Raj Kumar,
R. A. Mishra
Publication year - 2021
Publication title -
indonesian journal of electrical engineering and computer science
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.241
H-Index - 17
eISSN - 2502-4760
pISSN - 2502-4752
DOI - 10.11591/ijeecs.v22.i1.pp62-70
Subject(s) - adder , residue number system , detector , sign (mathematics) , arithmetic , computer science , digital signal processing , modulo , carry save adder , compiler , parallel computing , computer hardware , mathematics , discrete mathematics , telecommunications , mathematical analysis , programming language , latency (audio)
Magnitude comparison, sign detection and overflow detection are essential operations of residue number system (RNS) that are used in digital signal processing (DSP) applications. Moreover, sign detection attracts significant attention in RNS as it can also be used in division and magnitude comparison operations. However, these operations are not easy to perform in RNS. So, there is a need arise to propose a computationally advanced RNS based sign detector. This paper presents an area and power-efficient sign detection circuit for modulo {2 n - 1, 2 n , 2 n + 1} using mixed radix conversion technique. The proposed sign detector is constructed using a carry save adder (CSA), a modified parallel prefix adder and a carry-generation circuit. Based on the synthesized results using synopsys design compiler, the introduced design offers better results in terms of the area required and power consumption. Although, the speed will remain the same when compared to the recent sign detectors for the same moduli set.