
A streaming multi-class support vector machine classification architecture for embedded systems
Author(s) -
Jeevan Sirkunan,
Jia Tang,
Nasir Shaikh-Husin,
Muhammad Nadzir Marsono
Publication year - 2019
Publication title -
indonesian journal of electrical engineering and computer science
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.241
H-Index - 17
eISSN - 2502-4760
pISSN - 2502-4752
DOI - 10.11591/ijeecs.v16.i3.pp1286-1296
Subject(s) - bottleneck , computer science , support vector machine , field programmable gate array , throughput , embedded system , architecture , data stream mining , test data , computer hardware , real time computing , artificial intelligence , operating system , machine learning , art , visual arts , programming language , wireless
Pedestrian detection, face detection, speech recognition and object detection are some of the applications that have benefited from hardware-accelerated SVM. SVM classification computational complexity makes it challenging for designing hardware architecture with real-time performance and low power consumption. On an embedded streaming architecture, test data are stored on external memory and transferred in streams to the FPGA device. The hardware implementation for SVM classification needs to be fast enough to keep up with the data transfer speed. Prior implementation throttles data input to avoid overwhelming the computational unit. This results in a bottleneck in overall streaming architecture as maximum throughput could not be obtained. In this work, we propose a streaming architecture multi-class SVM classification for embedded system that is fully pipelined and able to process data continuously with out any need to throttle data stream input. The proposed design is targeted for embedded platform where test data is transferred in streams from an external memory. The architecture was implemented on Altera Cyclone IV platform. Performance analysis on our proposed architecture is done with regards to the number of features and support vectors. For validation, the results obtained is compared with LibSVM. The proposed architecture is able to produce output rate identical to test data input rate.