Open AccessTiming violation reduction in the FPGA prototyped design using failed path fixes and time borrowing techniques
Author(s) -
Salahuddin Savugathali,
Muslim Mustapa,
Mohammed Sharazel Razali,
Fazrul Faiz Zakaria
Publication year - 2019
Publication title -
indonesian journal of electrical engineering and computer science
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.241
H-Index - 17
eISSN - 2502-4760
pISSN - 2502-4752
DOI - 10.11591/ijeecs.v14.i2.pp628-636
Subject(s) - field programmable gate array , path (computing) , reduction (mathematics) , static timing analysis , computer science , embedded system , process (computing) , span (engineering) , computer hardware , real time computing , engineering , mathematics , civil engineering , geometry , programming language , operating system
A fascinating property of a latch-based design is that the combinational path delay is allowed to be longer than the clock cycle as it can borrow time from the shorter paths in the subsequent logic states. Time borrowing technique is a common method used to satisfy timing violation in an FPGA prototyped design. The purpose of this paper is to review the current methodology involved in SoC design prototyping using a Synopsys Protocompiler and HAPS-80 platform and propose an approach by fixing the failed path in a latch due to the gated clock conversion (GCC) process during the synthesis stage which could lead to the timing violation. Two techniques are applied in this paper namely time borrowing technique and our proposed technique, Failed Path Fixes to reduce the timing violation in the FPGA prototyped design. The result shows that the applied techniques are able to close the timing violation in the design with an average of 90% improvement.