Open AccessLinearity improvement of differential CMOS low noise amplifier
Author(s) -
Mohd Razali Muhamad,
Norhayati Soin,
Harikrishnan Ramiah
Publication year - 2019
Publication title -
indonesian journal of electrical engineering and computer science
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.241
H-Index - 17
eISSN - 2502-4760
pISSN - 2502-4752
DOI - 10.11591/ijeecs.v14.i1.pp407-412
Subject(s) - linearity , cmos , noise figure , electrical engineering , low noise amplifier , biasing , low voltage , electronic engineering , noise (video) , differential amplifier , amplifier , topology (electrical circuits) , physics , voltage , engineering , computer science , artificial intelligence , image (mathematics)
This paper presents the linearity improvement of differential CMOS low noise amplifier integrated circuit using 0.13um CMOS technology. In this study, inductively degenerated common source topology is adopted for wireless LAN application. The linearity of the single-ended LNA was improved by using differential structures with optimum biasing technique. This technique achieved better LNA and linearity performance compare with single-ended structure. Simulation was made by using the cadence spectre RF tool. Consuming 5.8mA current at 1.2V supply voltage, the designed LNA exhibits S 21 gain of 18.56 dB, noise figure (NF) of 1.85 dB, S 11 of −27.63 dB, S 22 of -34.33 dB, S 12 of −37.09 dB and IIP3 of -7.79 dBm.