Open AccessEfficient H.264 Decoder Architecture using External Memory and Pipelining
Author(s) -
G R Poornima,
S C Prasanna Kumar
Publication year - 2018
Publication title -
indonesian journal of electrical engineering and computer science
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.241
H-Index - 17
eISSN - 2502-4760
pISSN - 2502-4752
DOI - 10.11591/ijeecs.v12.i3.pp995-1002
Subject(s) - computer science , decoding methods , coding (social sciences) , video decoder , parallel computing , soft decision decoder , computer hardware , computer architecture , real time computing , algorithm , statistics , mathematics
A H.264 standard is one of the most popular coding standard with significant improvement in video broadcasting and streaming application. However it’s significant in compression but needs huge calculation and complex algorithm for providing better image quality and compression rate. In H.264 coding technique, designing of decoder is a key factor for efficient coding. In this paper we are designing a decoder using a complex input. We ensured several improvement like looping arrangement, buffer upgradation, buffer supplement, memory reusability and pipelining architecture. We have modified the memory structure also. Our designed decoder achieves a better frame decoding efficiency against state-of-art methods. The proposed approach also provides good area optimization with a maximum frequency of 355 MHz .