Open AccessA Comprehensive Review on Applications of Don’t Care Bit Filling Techniques for Test Power Reduction in Digital VLSI Systems
Author(s) -
Sourav Mitra,
Debaprasad Das
Publication year - 2018
Publication title -
indonesian journal of electrical engineering and computer science
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.241
H-Index - 17
eISSN - 2502-4760
pISSN - 2502-4752
DOI - 10.11591/ijeecs.v12.i3.pp941-949
Subject(s) - very large scale integration , dissipation , reliability engineering , computer science , power consumption , reliability (semiconductor) , embedded system , design flow , power (physics) , electronic engineering , engineering , physics , quantum mechanics , thermodynamics
Massive power consumption during VLSI testing is a serious threat to reliability concerns of ubiquitous silicon industry. A significant amount of low-power methodologies are proposed in the relevant literature to address this issue of test mode power consumption and don’t care bit(X) filling approaches are one of them in this fraternity. These don’t care(X) bit filling techniques have drawn the significant attention of industry and academia for its higher compatibility with existing design flow as neither modification of the CUT is required nor they need to rerun the time-consuming ATPG process. This paper presents an empirical survey of those X-bit filling techniques, applied to mitigate prime two types of dynamic power dissipation namely shift power and capture power, occurred during full scan testing.