Open AccessA SoC-IP Core Test Data Compression Scheme based on Error Correcting Hamming Codes
Author(s) -
Sourav Mitra,
Debaprasad Das
Publication year - 2018
Publication title -
indonesian journal of electrical engineering and computer science
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.241
H-Index - 17
eISSN - 2502-4760
pISSN - 2502-4752
DOI - 10.11591/ijeecs.v12.i3.pp933-940
Subject(s) - huffman coding , algorithm , hamming code , code word , data compression , computer science , compression ratio , mathematics , computer hardware , block code , decoding methods , engineering , internal combustion engine , automotive engineering
As system-on-chip (SoC) integration is growing very rapidly, increased circuit densities in SoC have lead a radical increase in test data volume and reduction of this large test data volume is one of the biggest challenges in the testing industry. This paper presents an efficient test independent compression scheme primarily based on the error correcting Hamming codes. The scheme operates on the pre-computed test data without the need of structural information of the circuit under test and thus it is applicable for IP cores in SoC. Test vectors are equally sliced into the size of ‘ n’ bits. Individual slices are treated as a Hamming codeword consisting of ‘ p’ parity bits and ‘ d’ data bits ( n = d + p) and validity of each codeword is verified. If a valid slice is encountered ’ data bits prefixed by ‘ 1’ are written to the compressed file, while for a non-valid slice all ‘ n’ bits preceded by ‘ 0’ are written to the compressed file. Finally, we apply Huffman coding and RLE in order to improve the compression ratio further The efficiency of the proposed hybrid scheme is verified with the experimental outcomes and comparisons to existing compression methods suitable for testing of IP cores.