Open AccessReducing Total Power Consumption and Total Area Techniques for Network-on-Chip Through Disable Cores and Routers Based on Clustering Method
Author(s) -
Ng Yen Phing,
Mohd Nazri Mohd Warip,
Phaklen Ehkan,
S.Y. Teo
Publication year - 2018
Publication title -
indonesian journal of electrical engineering and computer science
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.241
H-Index - 17
eISSN - 2502-4760
pISSN - 2502-4752
DOI - 10.11591/ijeecs.v10.i2.pp514-520
Subject(s) - network on a chip , cluster analysis , mesh networking , computer science , power consumption , span (engineering) , routing (electronic design automation) , topology (electrical circuits) , chip , network topology , power (physics) , embedded system , computer network , engineering , electrical engineering , telecommunications , physics , civil engineering , quantum mechanics , machine learning , wireless
Network-on-Chip (NoC) is a promising solution to overcome the communication problem of System-on-Chip (SoC) architecture. The execution of topology, routing algorithm and switching technique is significant because it powerfully affects the overall performance of NoC. In the Network-on-Chip, the total power consumption increasing due to the large scale of network. In order to solve it, a clustering method and disable cores and routers based on clustering method is apply onto mesh based NoC architecture. In the proposed approach, the optimization of total area and total power consumption are the major concern. Experiment results show that the proposed method outperformas the existing work. The clustering-mesh based method reduced the total area by 22% to 40 % and total power consumption by 22% to 56% compare to mesh topology. In addition, the proposed method by disable cores and routers based on clustering-mesh based method has decrease the total area by 45% to 87% and total power consumption by 33% to 75% compare to mesh topology.