Open AccessAn energy-aware system-on-chip architecture for intra prediction in HEVC standard
Author(s) -
Abdessamad El Ansari,
Anas Mansouri,
Ali Ahaitouf
Publication year - 2019
Publication title -
international journal of electrical and computer engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.277
H-Index - 22
ISSN - 2088-8708
DOI - 10.11591/ijece.v9i6.pp5084-5094
Subject(s) - computer science , field programmable gate array , architecture , block (permutation group theory) , embedded system , throughput , power consumption , computer hardware , software , chip , low energy , hardware architecture , system on a chip , hardware acceleration , computer architecture , power (physics) , operating system , wireless , art , telecommunications , physics , geometry , mathematics , atomic physics , quantum mechanics , visual arts
High resolution 4K and 8K are becoming the more used in video applications. Those resolutions are well supported in the new HEVC standard. Thus, embedded solutions such as development of dedicated ystems-On-Chips (SOC) to accelerate video processing on one chip instead of only software solutions are commendable. This paper proposes a novel parallel and high efficient hardware accelerator for the intra prediction block. This accelerator achieves a high-speed treatment due to pipelined processing units and parallel shaped architecture. The complexity of memory access is also reduced thanks to the proposed design with less increased power consumption. The implementation was performed on the 7 Series FPGA 28 nm technology resources on Zynq-7000 and results show, that the proposed architecture takes 16520 LUTs and can reach 143.65 MHz as a maximum frequency and it is able to support the throughput of 3840×2160 sequence at 90 frames per second.