Open AccessArea & Power Efficient VLSI Architecture of Mode Decision in Integer Motion Estimation for HEVC Video Coding Standard
Author(s) -
El Ansari Abdessamad,
Nejmeddine Bahri,
Azadeh Mansouri,
Nouri Masmoud,
Ali Ahaitouf
Publication year - 2019
Publication title -
international journal of electrical and computer engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.277
H-Index - 22
ISSN - 2088-8708
DOI - 10.11591/ijece.v9i4.pp2469-2480
Subject(s) - computer science , motion estimation , field programmable gate array , coding (social sciences) , hardware architecture , algorithm , computer hardware , very large scale integration , block (permutation group theory) , block size , real time computing , parallel computing , embedded system , key (lock) , software , mathematics , statistics , geometry , computer security , programming language
In this paper, we propose a new parallel hardware architecture for the mode decision algorithm, that it is based on the Sum Absolute of the Difference (SAD) for compute the motion estimation, which is the most critical algorithm in the recent video encoding standard HEVC. In fact, this standard introduced new large variable block sizes for the motion estimation algorithm and therefore the SAD requires a more reduced execution time in order to achieve the real time processing even for the ultra-high resolution sequences. The proposed accelerator executes the SAD algorithm in a parallel way for all sub-block prediction units (PUs) and coding unit (CU) whatever their sizes, which turns in a huge improvements in the performances, given that all the block sizes, PUs in each CU, are supported and processed in the same time. The Xilinx Artix-7 (Zynq-7000) FPGA is used for the prototyping and the synthesis of the proposed accelerator. The mode decision for motion estimation scheme is implemented with 32K LUTs, 50K registers and 108Kb BRAMs. The implementation results show that our hardware architecture can achieve 30 frames per second of the 4K (3840 × 2160) resolutions in real time processing at 115.15MHz.