Open AccessCMOS ring oscillator delay cell performance: a comparative study
Author(s) -
D. Abd Hadi,
Auzani Jidin,
Norfariza Ab Wahab,
Z Madiha,
Nurliyana Abd Mutalib,
Siti Halma Johari,
Suziana Ahmad,
M. Nuzaimah
Publication year - 2019
Publication title -
international journal of electrical and computer engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.277
H-Index - 22
ISSN - 2088-8708
DOI - 10.11591/ijece.v9i3.pp1757-1764
Subject(s) - ring oscillator , voltage controlled oscillator , delay line oscillator , computer science , phase locked loop , phase noise , topology (electrical circuits) , cmos , network topology , vackář oscillator , electronic engineering , control theory (sociology) , voltage , electrical engineering , engineering , control (management) , artificial intelligence , operating system
A common voltage-controlled oscillator (VCO) architecture used in the phase locked loop (PLL) is the ring oscillator (RO). RO consist of number of inverters cascaded together as the input of the first stage connected to the output of the last stage. It is important to design the RO to be work at desired frequency depend on application with low power consumption. This paper presents a review the performance evaluation of different delay cell topologies the implemented in the ring oscillator. The various topologies analyzed includes current starved delay cell, differential delay cell and current follower cell. Performance evaluation includes frequency range, frequency stability, phase noise and power consumption had been reviewed and comparison of different topologies has been discussed. It is observed that starved current delay cell have lower power consumption and the different of the frequency range is small as compared to other type of delay cell.