Open Access250 MHz Multiphase Delay Locked Loop for Low Power Applications
Author(s) -
Shruti Suman,
Kuldeep Sharma,
P. K. Ghosh
Publication year - 2017
Publication title -
international journal of electrical and computer engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.277
H-Index - 22
ISSN - 2088-8708
DOI - 10.11591/ijece.v7i6.pp3323-3331
Subject(s) - jitter , delay locked loop , cmos , physics , loop (graph theory) , electronic circuit , phase locked loop , power (physics) , electronic engineering , electrical engineering , optoelectronics , engineering , mathematics , combinatorics , quantum mechanics
Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential pair configuration is used for voltage controlled delay line (VCDL) implementation. This delay cell provides a high locking range with less phase noise and jitter due to differential pair configuration.For increasing the acquisition range and locking speed of the DLL, modified true single phase clock (TSPC) based phase frequency detector is used. The proposed design is implemented at 0.18 um CMOS technology and at power supply of 1.8 V . It has power consumption of 1.39 mW at 125 MHz center frequency with locking range from 0.5 MHz to 250 MHz.